The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 05, 2019
Filed:
Dec. 06, 2016
Applicant:
Renesas Electronics Corporation, Tokyo, JP;
Inventor:
Toshihiko Funaki, Kodaira, JP;
Assignee:
RENESAS ELECTRONICS CORPORATION, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/02 (2006.01); G11C 7/10 (2006.01); G11C 5/06 (2006.01); G11C 7/22 (2006.01); G11C 29/02 (2006.01); G11C 29/50 (2006.01);
U.S. Cl.
CPC ...
G11C 7/10 (2013.01); G11C 5/02 (2013.01); G11C 5/025 (2013.01); G11C 5/06 (2013.01); G11C 7/106 (2013.01); G11C 7/109 (2013.01); G11C 7/1087 (2013.01); G11C 7/22 (2013.01); G11C 29/023 (2013.01); G11C 29/025 (2013.01); G11C 29/028 (2013.01); G11C 29/50012 (2013.01); G11C 2207/229 (2013.01); G11C 2207/2218 (2013.01);
Abstract
A stack memory includes a base chip, a memory chip stacked over the base chip, and a viaprovided between the base chip and the memory chip. The base chip has an external interface circuit and a late write control circuit. The external interface circuit externally receives/transmits write data and read data. The late write control circuit has at least a register storing write data externally supplied through the external interface circuit. The memory chip has a memory cell array and a late write control circuit having at least a register storing write data supplied from the register through the via.