The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 05, 2019
Filed:
May. 15, 2010
Applicants:
Ernst Haselsteiner, Graz, AT;
Christian Kirchstaetter, Graz, AT;
Inventors:
Ernst Haselsteiner, Graz, AT;
Christian Kirchstaetter, Graz, AT;
Assignee:
NXP B.V., Eindhoven, NL;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/14 (2006.01); G06F 9/45 (2006.01); G06F 21/51 (2013.01); G06F 21/53 (2013.01); G06F 8/41 (2018.01); G06F 9/455 (2018.01); G06F 9/445 (2018.01);
U.S. Cl.
CPC ...
G06F 12/145 (2013.01); G06F 8/437 (2013.01); G06F 12/14 (2013.01); G06F 21/51 (2013.01); G06F 21/53 (2013.01); G06F 9/44589 (2013.01); G06F 9/45516 (2013.01); G06F 2221/2149 (2013.01);
Abstract
A computing device comprises: a memory; a processor; an interpreter; and a Memory Management Unit. The interpreter is for controlling the processor to execute a program comprising at least one first instruction in a format that is not native to the processor and at least one second instruction in machine code that is native to the processor. The Memory Management Unit is adapted to control access by the processor to the memory and possibly also to peripherals when the at least one second instruction is executed.