The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 2019

Filed:

Jul. 14, 2015
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Rama K. Hazari, Hyderabad, IN;

Sakethan R. Kotta, Hyderabad, IN;

Srinivas Kotta, Hyderabad, IN;

Eric N. Lais, Georgetown, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/10 (2016.01); G06F 12/1081 (2016.01); G06F 9/455 (2018.01);
U.S. Cl.
CPC ...
G06F 12/1081 (2013.01); G06F 9/45558 (2013.01); G06F 2009/45579 (2013.01); G06F 2009/45583 (2013.01);
Abstract

A system can translate an input/output (I/O) direct memory access (DMA) address to a physical system memory address in a data processing system. In response to receiving a DMA packet containing a requester identity (RID) associated with a partitionable endpoint (PE) number and an I/O DMA address, the system can retrieve an entry associated with the RID from a first translation validation table (TVT). Using that entry, the system can validate the number of TVT entries and extract from the I/O DMA address an offset. This offset can be validated and used to retrieve an entry in a second TVT. Data from this entry can be validated and the system can use this to access another table to retrieve the translation to the physical system memory address.


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