The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 2019

Filed:

Jul. 02, 2018
Applicants:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Ati Technologies Ulc, Markham, CA;

Inventors:

Vydhyanathan Kalyanasundharam, Santa Clara, CA (US);

Yaniv Adiri, Rishon LeZion, IL;

Philip Ng, Markham, CA;

Maggie Chan, Markham, CA;

Vincent Cueva, Markham, CA;

Anthony Asaro, Markham, CA;

Jimshed Mirza, Markham, CA;

Greggory D. Donley, Santa Clara, CA (US);

Bryan Broussard, Austin, TX (US);

Benjamin Tsien, Santa Clara, CA (US);

Assignees:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

ATI Technologies ULC, Markham, Ontario, CA;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/14 (2006.01); G06F 13/38 (2006.01); G06F 12/1009 (2016.01); G06F 12/12 (2016.01); G06F 12/1045 (2016.01);
U.S. Cl.
CPC ...
G06F 12/1009 (2013.01); G06F 12/1045 (2013.01); G06F 12/12 (2013.01); G06F 2212/684 (2013.01);
Abstract

A system including a gasket communicatively coupled between a unified northbridge (UNB) having a cache coherent interconnect (CCI) interface and a processor having an Advanced eXtensible Interface (AXI) coherency extension (ACE). The gasket is configured to translate requests from the processor that include ACE commands into equivalent CCI commands, wherein each request from the processor maps onto a specific CCI request type. The gasket is further configured to translate ACE tags into CCI tags. The gasket is further configured to translate CCI encoded probes from a system resource interface (SRI) into equivalent ACE snoop transactions. The gasket is further configured to translate the memory map to inter-operate with a UNB/coherent HyperTransport (cHT) environment. The gasket is further configured to receive a barrier transaction that is used to provide ordering for transactions.


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