The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 2019

Filed:

Jul. 30, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Jeffrey Carl Brownscheidle, Seattle, WA (US);

Sundeep Chadha, Austin, TX (US);

Maureen Anne Delaney, Burlington, VT (US);

Hung Qui Le, Austin, TX (US);

Dung Quoc Nguyen, Austin, TX (US);

Brian William Thompto, Austin, TX (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2018.01); G06F 9/30 (2018.01);
U.S. Cl.
CPC ...
G06F 9/3851 (2013.01); G06F 9/30189 (2013.01); G06F 9/3836 (2013.01); G06F 9/3887 (2013.01); G06F 9/3891 (2013.01);
Abstract

An execution slice circuit for a processor core has multiple parallel instruction execution slices and provides flexible and efficient use of internal resources. The execution slice circuit includes a master execution slice for receiving instructions of a first instruction stream and a slave execution slice for receiving instructions of a second instruction stream and instructions of the first instruction stream that require an execution width greater than a width of the slices. The execution slice circuit also includes a control logic that detects when a first instruction of the first instruction stream has the greater width and controls the slave execution slice to reserve a first issue cycle for issuing the first instruction in parallel across the master execution slice and the slave execution slice.


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