The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 2019

Filed:

Aug. 29, 2013
Applicant:

Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;

Inventor:

Minoru Saeki, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/302 (2018.01); G06F 21/75 (2013.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); H04L 9/00 (2006.01); G06F 21/55 (2013.01);
U.S. Cl.
CPC ...
G06F 9/3001 (2013.01); G06F 9/30181 (2013.01); G06F 9/3869 (2013.01); G06F 21/755 (2017.08); G06F 21/556 (2013.01); G06F 21/75 (2013.01); G06F 2221/2123 (2013.01); G06F 2221/2125 (2013.01); H04L 9/003 (2013.01);
Abstract

There is a need to provide a central processing unit capable of improving the resistance to power analysis attack without changing programs, lowering clock frequencies, and greatly redesigning a central processing unit of the related art. In a central processing unit, an arithmetic unit is capable of performing arithmetic operation using data irrelevant to data stored in a register group. A control unit allows the arithmetic unit to perform arithmetic processing corresponding to an incorporated instruction. At this time, the control unit allows the arithmetic unit to perform arithmetic processing using the irrelevant data during a first one-clock cycle.


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