The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 26, 2019

Filed:

Mar. 01, 2018
Applicant:

Iowa State University Research Foundation, Inc., Ames, IA (US);

Inventors:

Yuming Zhuang, Ames, IA (US);

Degang James Chen, Ames, IA (US);

Benjamin Magstadt, Lincoln, NE (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/10 (2006.01); H03M 1/06 (2006.01); H03M 1/56 (2006.01); H03M 1/66 (2006.01);
U.S. Cl.
CPC ...
H03M 1/1023 (2013.01); H03M 1/0607 (2013.01); H03M 1/56 (2013.01); H03M 1/66 (2013.01);
Abstract

The present disclosure relates to a digital-to-analog converter (DAC) linearization system including a DAC, a summing buffer structure, an analog-to-digital converter (ADC), a calculation system, an error look-up table, and an adder. A combination of the DAC, the summing buffer structure, and the ADC sequentially provide first and second ADC output signals, both of which include DAC integral nonlinearity (INL). The calculation system calculates the DAC INL based on the first and second ADC output signals, the error look-up table provides a correction signal mapping to the calculated DAC INL, and the adder provides a calibrated digital input signal to the DAC based on the correction signal. The calibrated digital input signal ensures the DAC to generate an updated output signal with less nonlinearity and improved purity.


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