The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 26, 2019

Filed:

Jul. 05, 2017
Applicant:

Dongbu Hitek Co., Ltd., Seoul, KR;

Inventors:

Young Seok Kim, Gyeonggi-do, KR;

Bum Seok Kim, Seoul, KR;

Assignee:

DB Hitek Co., Ltd, Seoul, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/265 (2006.01); H01L 21/311 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7811 (2013.01); H01L 21/26513 (2013.01); H01L 21/31111 (2013.01); H01L 29/0634 (2013.01); H01L 29/0696 (2013.01); H01L 29/66666 (2013.01); H01L 29/66712 (2013.01); H01L 29/7827 (2013.01); H01L 29/4236 (2013.01); H01L 29/7813 (2013.01);
Abstract

A super junction MOSFET includes a substrate having a first conductive type, an epitaxial layer formed on the substrate, a set of pillars extending from the substrate through the epitaxial layer, the set of pillars being spaced apart from each other, a set of first wells, the set of first wells formed in the epitaxial layer to extend to an upper face of the epitaxial layer, and each of the set of first wells connected to at least one corresponding pillar of the set of pillars, a set of second wells of the first conductive type formed in the set of first wells, and a plurality of gate structures formed on the epitaxial layer, each extending in a first direction to have a stripe shape such that the gate structures are spaced apart from each other. Thus, the gate structure has a relatively small area to reduce an input capacitance of the super junction MOSFET.


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