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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10217839 B1

PDFFull Text
Date of Patent:
Feb. 26, 2019

Filed:

Mar. 24, 2017

Field effect transistor (fet) with a gate having a recessed work function metal layer and method of forming the fet

Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Chanro Park, Clifton Park, NY (US);

Kisup Chung, Slingerlands, NY (US);

Victor Chan, Guilderland, NY (US);

Koji Watanabe, Voorheesville, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:

Gibb & Riley, LLC

Anthony J. Canale

Primary Examiner:

Chandra Chaudhari

Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/49 (2006.01); H01L 29/417 (2006.01); H01L 21/3105 (2006.01); H01L 21/3213 (2006.01); H01L 21/768 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 21/28079 (2013.01); H01L 21/28088 (2013.01); H01L 21/31053 (2013.01); H01L 21/32133 (2013.01); H01L 21/76897 (2013.01); H01L 29/41775 (2013.01); H01L 29/42376 (2013.01); H01L 29/4958 (2013.01); H01L 29/4966 (2013.01);
Abstract

Disclosed is a field effect transistor (FET) with a replacement metal gate (RMG) and a method of forming the FET. The RMG includes a conformal gate dielectric layer and a stack of gate conductor layers on the gate dielectric layer. The stack includes a conformal work function metal (WFM) layer and a conductive fill material (CFM) layer on the WFM layer. Within the stack, the top surface of the CFM layer is above the level of the top of an adjacent vertical portion of the WFM layer. A dielectric gate cap has a center portion and an edge portion. The center portion is above the top surface of the CFM layer and the edge portion is above the top of the adjacent vertical portion of the WFM layer and is further positioned laterally immediately adjacent to an upper portion of an outer sidewall of the CFM layer.

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