The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 26, 2019

Filed:

Dec. 08, 2016
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Markus Zundel, Egmating, DE;

Thomas Ostermann, Velden am Wörthersee, AT;

Michael Sorger, Villach, AT;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/417 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/739 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/41775 (2013.01); H01L 29/0696 (2013.01); H01L 29/1083 (2013.01); H01L 29/401 (2013.01); H01L 29/407 (2013.01); H01L 29/41741 (2013.01); H01L 29/41766 (2013.01); H01L 29/4236 (2013.01); H01L 29/4238 (2013.01); H01L 29/7813 (2013.01); H01L 29/7397 (2013.01); H01L 29/7827 (2013.01);
Abstract

A semiconductor device includes a plurality of trenches extending into a semiconductor substrate. Each trench comprises a plurality of enlarged width regions distributed along the trench. At least one electrically conductive trench structure is located in each trench. The semiconductor device comprises an electrically insulating layer arranged between the semiconductor substrate and an electrode structure. The semiconductor device comprises a vertical electrically conductive structure extending through the electrically insulating layer. The vertical electrically conductive structure forms an electrically connection between the electrode structure and an electrically conductive trench structure located in a first trench of at a first enlarged width region. The electrically insulating layer is arranged between a second enlarged width region of the plurality of enlarged width regions of the first trench and an electrode structure above the second enlarged width region without any vertical electrical connections through the electrically insulating layer at the second enlarged width region.


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