The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 26, 2019

Filed:

Jul. 11, 2016
Applicant:

Osram Opto Semiconductors Gmbh, Regensburg, DE;

Inventors:

Korbinian Perzlmaier, Regensburg, DE;

Lutz Hoeppel, Alteglofsheim, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/00 (2010.01); H01L 33/48 (2010.01); H01L 21/22 (2006.01); H01L 27/15 (2006.01); H01L 33/38 (2010.01); H01L 33/40 (2010.01); H01L 33/44 (2010.01); H01L 29/872 (2006.01); H01L 33/62 (2010.01); H01L 33/20 (2010.01); H01L 33/30 (2010.01); H01L 33/42 (2010.01); H01L 29/16 (2006.01); H01L 29/24 (2006.01); H01L 33/32 (2010.01);
U.S. Cl.
CPC ...
H01L 27/15 (2013.01); H01L 29/872 (2013.01); H01L 33/382 (2013.01); H01L 33/387 (2013.01); H01L 33/40 (2013.01); H01L 33/44 (2013.01); H01L 33/62 (2013.01); H01L 29/1604 (2013.01); H01L 29/247 (2013.01); H01L 33/20 (2013.01); H01L 33/30 (2013.01); H01L 33/32 (2013.01); H01L 33/42 (2013.01); H01L 2933/0016 (2013.01); H01L 2933/0025 (2013.01); H01L 2933/0066 (2013.01);
Abstract

The invention relates to a method for producing an optoelectronic semiconductor chip (). A semiconductor layer sequence () is provided, comprising a first semiconductor layer () and a second semiconductor layer (). Furthermore, a first contact layer () is provided which extends laterally along the first semiconductor layer () and electrically contacts same. A third semiconductor layer () is applied onto a first contact layer () face facing away from the semiconductor layer sequence (). A recess () is formed which extends through the third semiconductor layer (), the first contact layer (), and the first semiconductor layer () into the second semiconductor layer (). A passivation layer () is applied onto a third semiconductor layer () face facing away from the semiconductor layer sequence (). At least one first () and at least one second passage opening () are formed in the passivation layer (). A second contact layer () is applied which electrically contacts the second semiconductor layer () in the region of the at least one first passage opening () and the third semiconductor layer () in the region of the at least one second passage opening (). The invention additionally relates to an optoelectronic semiconductor chip ().


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