The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 26, 2019

Filed:

Oct. 26, 2017
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Jin Cai, Cortlandt Manor, NY (US);

Jean-Olivier Plouchart, New York, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/01 (2006.01); H01L 27/12 (2006.01); H01L 21/027 (2006.01); H01L 21/70 (2006.01); H01L 21/762 (2006.01); H01L 21/84 (2006.01); H01L 21/306 (2006.01); H01L 21/02 (2006.01); H01L 27/13 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1203 (2013.01); H01L 21/0273 (2013.01); H01L 21/02238 (2013.01); H01L 21/30604 (2013.01); H01L 21/30625 (2013.01); H01L 21/76254 (2013.01); H01L 21/84 (2013.01); H01L 27/13 (2013.01);
Abstract

A radio frequency fully depleted silicon on insulator (RF-FDSOI) device and method of fabrication are provided. A silicon wafer for digital circuits is constructed using fully depleted silicon on insulator technology having a thin buried oxide layer. Localized areas of the silicon wafer are constructed for radio frequency circuits and/or passive devices. The silicon wafer has a silicon substrate having a resistivity greater than 1 KΩ·cm. The localized areas of the silicon wafer may include a trap rich layer implanted underneath a thin buried oxide layer. The localized areas of the silicon wafer may include a buried oxide layer that is thicker than the thin buried oxide layer. The thicker oxide layer is between 20 and 2000 nm thick. The localized areas of the silicon wafer may include a trap rich layer implanted underneath the thicker buried oxide layer.


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