The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 26, 2019

Filed:

Jan. 25, 2017
Applicant:

Fuji Electric Co., Ltd., Kawasaki, JP;

Inventors:

Hiroshi Kanno, Matsumoto, JP;

Hitoshi Sumida, Matsumoto, JP;

Masaharu Yamaji, Matsumoto, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 21/76 (2006.01); H01L 21/84 (2006.01); H01L 23/00 (2006.01); H01L 27/04 (2006.01); H01L 27/08 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 21/822 (2006.01); H01L 23/498 (2006.01); H01L 27/092 (2006.01); H03K 17/687 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1203 (2013.01); H01L 21/76 (2013.01); H01L 21/822 (2013.01); H01L 21/8238 (2013.01); H01L 21/84 (2013.01); H01L 23/49838 (2013.01); H01L 24/32 (2013.01); H01L 27/04 (2013.01); H01L 27/08 (2013.01); H01L 27/092 (2013.01); H01L 29/0646 (2013.01); H01L 29/0649 (2013.01); H01L 29/1095 (2013.01); H03K 17/687 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/32227 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48106 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/48465 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/1426 (2013.01);
Abstract

A semiconductor integrated circuit includes a semiconductor layer of a first conductivity type which is stacked on a support substrate with an insulating layer interposed between the semiconductor layer and the support substrate, a first well region of a second conductivity type buried in an upper part of the semiconductor layer so as to be separated from the insulating layer, a second well region of the first conductivity type buried in an upper part of the first well region, and an isolation region of the first conductivity type buried in the upper part of the semiconductor layer such that the isolation region surrounds the first well region and is separated from the first well region and the insulating layer.


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