The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 26, 2019

Filed:

May. 16, 2017
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Olivier Tesson, Bretteville l'Orgueilleuse, FR;

Thomas Francois, Benouville, FR;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/62 (2006.01); H01L 27/02 (2006.01); H01L 29/06 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0292 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 27/0207 (2013.01); H01L 27/0266 (2013.01); H01L 29/0649 (2013.01); H01L 29/0692 (2013.01); H01L 29/41725 (2013.01); H01L 29/41758 (2013.01);
Abstract

A semiconductor switch device and a method of making the same. The semiconductor switch device includes a field effect transistor located on a semiconductor substrate. The field effect transistor includes a plurality of gates. Each gate includes a gate electrode and gate dielectric arranged in a loop on a major surface of the substrate. The loops formed by the gates are arranged concentrically. Each gate has a source region located adjacent an inner edge or outer edge of the loop formed by that gate and a drain region located adjacent the other edge of said inner edge and said outer edge of the loop formed by that gate.


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