The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 26, 2019
Filed:
Aug. 30, 2016
Semiconductor Components Industries, Llc, Phoenix, AZ (US);
David D. Marreiro, Oakland, CA (US);
Yupeng Chen, San Jose, CA (US);
Steven M. Etter, Phoenix, AZ (US);
Umesh Sharma, San Jose, CA (US);
SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Phoenix, AZ (US);
Abstract
An ultra-low capacitance ESD protection device with an ultra-fast response time and a low turn-on voltage, and a high holding current. The device may include: a heavily-doped p-type substrate; a lightly-doped n-type epitaxial layer with a heavily-doped n-type buried layer; and a semiconductor-controlled rectifier (SCR) structure within the epitaxial layer. The SCR structure includes, between a ground terminal and a pad terminal: a shallow P+ region within a moderately-doped n-type well to form an emitter-base junction of a trigger transistor; a shallow N+ region within a moderately-doped p-type well to form an emitter-base junction of a latching transistor, and a PN junction coupled to either of the shallow regions as a forward-biased series diode. To reduce capacitance, the n-type and p-type wells are separated by a lightly-doped portion of the epitaxial layer having a small lateral dimension for enhanced switching speed.