The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 26, 2019

Filed:

Aug. 10, 2016
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Shinya Fukayama, Nagoya Aichi, JP;

Naoyuki Komuta, Oita Oita, JP;

Hiroshi Watabe, Yokkaichi Mie, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/00 (2006.01); H01L 21/66 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 22/12 (2013.01); H01L 22/20 (2013.01); H01L 24/81 (2013.01); H01L 25/50 (2013.01); H01L 2224/81908 (2013.01); H01L 2225/06513 (2013.01);
Abstract

A method for manufacturing a semiconductor device including a plurality of semiconductor chips includes steps of placing, on a first semiconductor chip, a second semiconductor chip, such that a plurality of bumps is located between the first semiconductor chip and the second semiconductor chip, determining a distance between the first semiconductor chip and the second semiconductor chip, and determining whether or not the distance is within a predetermined range and stopping placement of additional chips if the distance is determined to be outside the predetermined range.


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