The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 26, 2019

Filed:

Jan. 04, 2017
Applicant:

Mie Fujitsu Semiconductor Limited, Kuwana, Mie, JP;

Inventors:

Scott E. Thompson, Gainesville, FL (US);

Damodar R. Thummalapally, Milipitas, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 21/84 (2006.01); H01L 27/02 (2006.01); H01L 27/11 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/265 (2006.01); H01L 21/02 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823412 (2013.01); H01L 21/0262 (2013.01); H01L 21/26513 (2013.01); H01L 21/823481 (2013.01); H01L 21/823493 (2013.01); H01L 21/823807 (2013.01); H01L 21/823892 (2013.01); H01L 21/84 (2013.01); H01L 27/0207 (2013.01); H01L 27/0921 (2013.01); H01L 27/11 (2013.01); H01L 27/1104 (2013.01); H01L 29/0653 (2013.01); H01L 29/105 (2013.01); H01L 29/1079 (2013.01); H01L 29/1083 (2013.01); H01L 29/66545 (2013.01); H01L 29/66568 (2013.01); H01L 29/66628 (2013.01); H01L 29/7834 (2013.01); H01L 29/7838 (2013.01);
Abstract

Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVcompared to conventional bulk CMOS and can allow the threshold voltage Vof FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.


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