The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 26, 2019

Filed:

Oct. 30, 2017
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Soojung Choi, Seoul, KR;

Moonkyun Song, Anyang-si, KR;

Yoon Tae Hwang, Seoul, KR;

Kyumin Lee, Seoul, KR;

Sangjin Hyun, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 21/8238 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 21/306 (2006.01); H01L 21/3213 (2006.01); H01L 21/311 (2006.01); H01L 21/324 (2006.01); H01L 27/092 (2006.01); H01L 29/51 (2006.01); H01L 21/3105 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28185 (2013.01); H01L 21/28202 (2013.01); H01L 21/30604 (2013.01); H01L 21/31053 (2013.01); H01L 21/31144 (2013.01); H01L 21/324 (2013.01); H01L 21/32139 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823828 (2013.01); H01L 21/823857 (2013.01); H01L 27/0922 (2013.01); H01L 27/0924 (2013.01); H01L 29/4958 (2013.01); H01L 29/4966 (2013.01); H01L 29/513 (2013.01); H01L 29/66545 (2013.01);
Abstract

A method of fabricating a semiconductor device includes forming first and second gate dielectric layers on first and second regions of a semiconductor substrate, respectively, forming a first metal-containing layer on the first and second gate dielectric layers, performing a first annealing process with respect to the first metal-containing layer, removing the first metal-containing layer from the first region, forming a second metal-containing layer on an entire surface of the semiconductor substrate, performing a second annealing process with respect to the second metal-containing layer, forming a gate electrode layer on the second metal-containing layer, and partially removing the gate electrode layer, the second metal-containing layer, the first metal-containing layer, the first gate dielectric layer, and the second gate dielectric layer to form first and second gate patterns on the first and second regions, respectively.


Find Patent Forward Citations

Loading…