The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 26, 2019

Filed:

Dec. 06, 2017
Applicant:

Werlatone, Inc., Brewster, NY (US);

Inventors:

Allen F. Podell, Palo Alto, CA (US);

Ky-Hien Do, Mississauga, CA;

Assignee:

Werlatone, Inc., Patterson, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01G 4/30 (2006.01); H01G 4/232 (2006.01); H01G 4/12 (2006.01); H01G 4/012 (2006.01); H01G 4/38 (2006.01); H01G 4/40 (2006.01); H01G 2/06 (2006.01); H01G 4/228 (2006.01); H05K 1/18 (2006.01);
U.S. Cl.
CPC ...
H01G 4/30 (2013.01); H01G 2/06 (2013.01); H01G 4/012 (2013.01); H01G 4/12 (2013.01); H01G 4/228 (2013.01); H01G 4/232 (2013.01); H01G 4/38 (2013.01); H01G 4/40 (2013.01); H05K 1/181 (2013.01);
Abstract

A multilayer capacitor may include a capacitor stack having pluralities of first and second plate electrodes connected to respective stack face terminals. Two face terminals on different stack sides are connected to the first plate electrodes. Two different face terminals also on different stack sides are connected to the second plate electrodes. Respective base conductors connect to the two sets of face terminals for connecting the capacitor to an external circuit. Three face terminals may be connected to the first or second plate electrodes. The base conductors may connect to the face terminals at the same relative position of the capacitor stack, at different relative positions of the capacitor stack. A capacitor stack may be positioned with a stack end facing a base substrate. Two multilayer capacitors may be mounted electrically in parallel with one or more lossy elements spanning a gap between the capacitors.


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