The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 26, 2019

Filed:

Jun. 15, 2017
Applicant:

Silicon Display Technology, Yongin-si, KR;

Inventors:

Kijoong Kim, Suwon-si, KR;

Young Man Park, Gwangju-si, KR;

Ji Ho Hur, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/20 (2006.01); H03K 19/0175 (2006.01);
U.S. Cl.
CPC ...
G09G 3/2092 (2013.01); G09G 3/20 (2013.01); H03K 19/0175 (2013.01); G09G 2300/0408 (2013.01); G09G 2310/0289 (2013.01); G09G 2310/0297 (2013.01);
Abstract

The present invention relates to a level shifter including: a first inverter applied with a first voltage and a second voltage of different polarities and operated depending on an input voltage to output a first inverting output signal; a second inverter applied with the first voltage and the second voltage and operated depending on the first inverting output signal to output a second inverting output signal having an opposite polarity to that of the first inverting output signal; a driver applied with a third voltage and a fourth voltage, including a first load transistor having the first inverting output signal as a gate input and a second load transistor having a fifth voltage as the gate input, and outputting an output voltage having an increased level with respect to the input voltage; and a bootstrap capacitor positioned between an output terminal of the second inverter and a gate electrode of the second load transistor to help the fifth voltage to be bootstrapped depending on the second inverting output signal, and an array apparatus including the same.


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