The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 26, 2019

Filed:

Oct. 19, 2016
Applicant:

Ersa Gmbh, Wertheim, DE;

Inventors:

Udo Hofmann, Roellbach, DE;

Wolfram Sinn, Offenbach, DE;

Sergei Richter, Neckartenzlingen, DE;

Assignee:

ERSA GmbH, Wertheim, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06T 7/00 (2017.01); G06T 7/73 (2017.01); H05K 13/00 (2006.01); H05K 13/04 (2006.01); H05K 13/08 (2006.01);
U.S. Cl.
CPC ...
G06T 7/001 (2013.01); G06T 7/74 (2017.01); H05K 13/0053 (2013.01); H05K 13/0486 (2013.01); H05K 13/089 (2018.08); H05K 13/0818 (2018.08); H05K 13/0853 (2018.08); G06T 2207/30141 (2013.01);
Abstract

A method for placing electronic components onto a circuit board, comprising the following steps: Placing a component to be placed of a first component type into a starting position; creating a component image of the component to be placed in the starting position; creating a circuit board region image of a circuit board of a first circuit board region type; calculating a travel path for moving the component to be placed into a final position on the circuit board based upon an image overlay of the component image and a previously saved reference component image of a reference component of the first component type, and based upon a previously saved reference travel path of the reference component from a reference starting position into a reference final position on a reference circuit board of the first circuit board region type, and based upon an image overlay of the circuit board region image and a previously saved reference circuit board region image of the reference circuit board; moving the component to be placed along the travel path into the final position.


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