The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 26, 2019

Filed:

Dec. 07, 2017
Applicant:

Agiga Tech Inc., San Diego, CA (US);

Inventors:

Ronald H Sartore, Valley Center, CA (US);

Thomas O. Koger, San Diego, CA (US);

Assignee:

AgigA Tech Inc., San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/42 (2006.01); G06F 13/364 (2006.01); G06F 12/0802 (2016.01); G06F 12/1009 (2016.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4234 (2013.01); G06F 3/065 (2013.01); G06F 3/0613 (2013.01); G06F 3/0619 (2013.01); G06F 3/0647 (2013.01); G06F 3/0688 (2013.01); G06F 12/0802 (2013.01); G06F 12/1009 (2013.01); G06F 13/364 (2013.01); G06F 2212/60 (2013.01);
Abstract

A memory module is organized into slice sections, each configured to input and output a slice of data for a different section of a data bus. Each slice section includes at least one nonvolatile memory (NVM) and a memory element, such as random access volatile memory, to store the slice of data for the slice section during operations that transfer the slice of data between the section of the data bus for the slice section and the NVM of the slice section. Each slice section also includes a slice controller configured to translate an address for the slice of data for the section of the data bus into a physical address of the NVM of the slice section.


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