The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 26, 2019
Filed:
May. 01, 2017
Nvidia Corporation, Santa Clara, CA (US);
Jerome F. Duluk, Jr., Palo Alto, CA (US);
John Mashey, Portola Valley, CA (US);
Mark Hairgrove, San Jose, CA (US);
Chenghuan Jia, Fremont, CA (US);
Cameron Buschardt, Round Rock, TX (US);
Lucien Dunning, Santa Clara, CA (US);
Brian Fahs, Los Altos, CA (US);
NVIDIA CORPORATION, Santa Clara, CA (US);
Abstract
Techniques are provided by which memory pages may be migrated among PPU memories in a multi-PPU system. According to the techniques, a UVM driver determines that a particular memory page should change ownership state and/or be migrated between one PPU memory and another PPU memory. In response to this determination, the UVM driver initiates a peer transition sequence to cause the ownership state and/or location of the memory page to change. Various peer transition sequences involve modifying mappings for one or more PPU, and copying a memory page from one PPU memory to another PPU memory. Several steps in peer transition sequences may be performed in parallel for increased processing speed.