The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 26, 2019

Filed:

Jan. 20, 2016
Applicants:

Dae-kwon Kang, Yongin-si, KR;

Ji-young Jung, Hwaseong-si, KR;

Dong-gyun Kim, Seoul, KR;

Jae-seok Yang, Hwaseong-si, KR;

Sung-keun Park, Goyang-si, KR;

Young-gook Park, Seongnam-si, KR;

Inventors:

Dae-kwon Kang, Yongin-si, KR;

Ji-Young Jung, Hwaseong-si, KR;

Dong-Gyun Kim, Seoul, KR;

Jae-Seok Yang, Hwaseong-si, KR;

Sung-Keun Park, Goyang-si, KR;

Young-Gook Park, Seongnam-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G21K 5/00 (2006.01); G03F 1/00 (2012.01); G03F 7/00 (2006.01); G03F 1/70 (2012.01); G03F 7/20 (2006.01);
U.S. Cl.
CPC ...
G03F 1/70 (2013.01); G03F 7/70433 (2013.01); G03F 7/70466 (2013.01); G03F 1/00 (2013.01); G06F 17/5072 (2013.01); G06F 17/5081 (2013.01); G06F 2217/12 (2013.01); G21K 5/00 (2013.01);
Abstract

According to example embodiments of inventive concepts, a layout design system includes a processor, a storage unit configured to store a layout design, and a stitch module. The layout design includes a first pattern group and a second pattern group disposed in accordance with a design. The first pattern group including a first pattern for patterning at a first time. The second pattern group including a second pattern for patterning at a second time that is different than the first time. The stitch module is configured to detect an iso-pattern of the second pattern using the processor. The stitch module is configured to repetitively designate at least one of the first pattern, which is spaced apart from the iso-pattern by a pitch or more, to the second pattern group using the processor.


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