The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 26, 2019

Filed:

Jul. 27, 2016
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Sean M. Carey, Hyde Park, NY (US);

Kirk D. Peterson, Jericho, VT (US);

Andrew A. Turner, Underhill, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/3177 (2006.01); G01R 31/317 (2006.01); G06F 1/08 (2006.01); G01R 31/3185 (2006.01); G06F 17/50 (2006.01); G06F 1/3206 (2019.01); G06F 1/324 (2019.01); G06F 1/3296 (2019.01); G01R 31/3183 (2006.01);
U.S. Cl.
CPC ...
G01R 31/3177 (2013.01); G01R 31/31703 (2013.01); G01R 31/31704 (2013.01); G01R 31/31725 (2013.01); G01R 31/31727 (2013.01); G01R 31/318522 (2013.01); G01R 31/318525 (2013.01); G01R 31/318552 (2013.01); G06F 1/08 (2013.01); G06F 1/324 (2013.01); G06F 1/3206 (2013.01); G06F 1/3296 (2013.01); G06F 17/50 (2013.01); G01R 31/318342 (2013.01);
Abstract

Embodiments are directed to a method and system for testing and optimizing integrated circuit devices. Latches within an integrated circuit device that fail to operate properly are found using observed data from a test. Thereafter, a directed graph of the layout of the integrated circuit is used to find clock controllers that feed into the latches. The clock controllers that are the most likely to be at issue are ranked, then testing can be performed to confirm that a critical path can be found. The critical path can be excluded from further power optimization to maintain the performance of the integrated circuit device. Other embodiments are also disclosed.


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