The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 19, 2019
Filed:
Apr. 07, 2016
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Inventors:
Iksung Park, Seoul, KR;
Heeyoub Kang, Seoul, KR;
Young-Min Kim, Seongnam-si, KR;
Eunji You, Yongin-si, KR;
Hwi-jong Yoo, Seoul, KR;
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/02 (2006.01); H05K 3/00 (2006.01); H01L 23/60 (2006.01); H01L 25/065 (2006.01); H01L 25/18 (2006.01); H01L 23/538 (2006.01); G11C 5/02 (2006.01); G11C 5/04 (2006.01); G11C 5/00 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0259 (2013.01); G11C 5/025 (2013.01); G11C 5/04 (2013.01); H01L 23/5386 (2013.01); H01L 23/60 (2013.01); H01L 25/0655 (2013.01); H01L 25/18 (2013.01); H05K 3/0052 (2013.01); G11C 5/005 (2013.01); H05K 1/0268 (2013.01); H05K 2201/10159 (2013.01);
Abstract
Disclosed is a printed circuit hoard. The printed circuit board includes a plurality of insulation layers and a plurality of pattern layers alternately stacked. The printed circuit board includes a plurality of device areas on which semiconductor packages are mounted and a peripheral area adjacent the device areas. An electrostatic discharge pattern is in a respective pattern layer among the plurality of pattern layers and is disposed at a boundary region between a respective device area of the plurality of device areas and the peripheral area.