The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 19, 2019

Filed:

Mar. 09, 2017
Applicant:

Fortinet, Inc., Sunnyvale, CA (US);

Inventors:

Zhiwei Dai, Campbell, CA (US);

Xu Zhou, San Jose, CA (US);

Assignee:

Fortinet, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/22 (2006.01); H04L 29/06 (2006.01); G06F 13/34 (2006.01); G06F 13/16 (2006.01); G06F 13/28 (2006.01); G06F 9/48 (2006.01); G06F 15/78 (2006.01); H04L 12/26 (2006.01);
U.S. Cl.
CPC ...
H04L 63/0209 (2013.01); G06F 9/4887 (2013.01); G06F 13/1673 (2013.01); G06F 13/225 (2013.01); G06F 13/28 (2013.01); G06F 13/34 (2013.01); G06F 15/7825 (2013.01); H04L 43/08 (2013.01); H04L 43/16 (2013.01); H04L 63/0272 (2013.01); G06F 2213/2408 (2013.01); G06F 2213/2804 (2013.01);
Abstract

Systems and methods for limiting the rate of packet transmission from a NIC to a host CPU are provided. According to one embodiment, data packets are received from a network by the NIC. The NIC is coupled to a host central processing unit (CPU) of a network security device through a bus. A status of the host CPU is monitored by the NIC. A rate limiting mode indicator is set by the NIC based on the status. When the rate limiting mode indicator indicates rate limiting is inactive, then the received data packets are delivered or made available to the host CPU for processing. When the rate limiting mode indicator indicates rate limiting is active, then rate limiting is performing by temporarily stopping or slowing the delivery or making available of the received data packets to the host CPU for processing.


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