The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 19, 2019

Filed:

Dec. 30, 2016
Applicant:

Xockets, Inc., San Jose, CA (US);

Inventors:

Parin Bhadrik Dalal, Milpitas, CA (US);

Stephen Paul Belair, Santa Cruz, CA (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/18 (2006.01); H04L 12/851 (2013.01); G06F 13/16 (2006.01); H04L 12/801 (2013.01); H04L 29/06 (2006.01); G06F 13/28 (2006.01); G06F 21/55 (2013.01); H04L 12/931 (2013.01); G06F 13/364 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
H04L 47/2441 (2013.01); G06F 13/1605 (2013.01); G06F 13/1652 (2013.01); G06F 13/1673 (2013.01); G06F 13/28 (2013.01); G06F 13/364 (2013.01); G06F 13/404 (2013.01); G06F 13/4022 (2013.01); G06F 13/4234 (2013.01); G06F 21/55 (2013.01); H04L 29/06 (2013.01); H04L 47/10 (2013.01); H04L 49/70 (2013.01); H04L 63/0227 (2013.01); Y02D 10/14 (2018.01); Y02D 10/151 (2018.01);
Abstract

A distributed computing architecture for executing at least first and second computing operations executed in parallel on a set of data, can include a plurality of servers, including first servers that each include at least one central processing unit (CPU), and at least one offload processing module coupled to CPU by a bus. Each offload processing module can include computation elements. The computation elements can be configured to operate as a virtual switch, and to execute the second computing operations on first processed data to generate second processed data. The virtual switches can form a switch fabric for exchanging data between the offload processing modules. The second computing operations are executed on a plurality of the offload processing modules in parallel.


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