The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 19, 2019

Filed:

Mar. 19, 2018
Applicant:

SK Hynix Inc., Icheon-si, Gyeonggi-do, KR;

Inventor:

Kwang Hun Lee, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/15 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03K 5/15 (2013.01); H03K 2005/00019 (2013.01);
Abstract

An input buffer circuit is disclosed, which relates to a technology for a receiver circuit including a plurality of input buffers having different characteristics. The input buffer circuit includes a first buffer configured to output a first input signal by buffering a command address received based on a flag signal, a second buffer configured to output a second input signal by buffering the command address based on the flag signal, a first delay matching circuit configured to output a first matching signal by delaying the first input signal by a first delay time, a second delay matching circuit configured to output a second matching signal by delaying the second input signal by a second delay time, and a selection circuit configured to select any one of the first matching signal and the second matching signal based on a selection signal.


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