The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 19, 2019

Filed:

Aug. 05, 2016
Applicant:

Imec Vzw, Leuven, BE;

Inventors:

Jan Van Houdt, Bekkevoort, BE;

Voon Yew Thean, Brussels, BE;

Assignee:

IMEC vzw, Leuven, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/51 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/516 (2013.01); H01L 21/28291 (2013.01); H01L 29/6684 (2013.01); H01L 29/78391 (2014.09); H01L 21/0242 (2013.01); H01L 21/02425 (2013.01); H01L 21/02568 (2013.01);
Abstract

The disclosed technology generally relates to semiconductor devices, and more particularly to a non-volatile ferroelectric memory device and to methods of fabricating the same. In one aspect, a non-volatile memory device includes a high dielectric constant layer (high-k) layer or a metal layer on a semiconductor substrate. The non-volatile memory device additionally includes a two-dimensional (2D) semiconductor channel layer interposed between the high-k layer or metal layer and a ferroelectric layer. The non-volatile memory device additionally includes a metal gate layer on the ferroelectric layer, and further includes a source region and a drain region each electrically coupled to the 2D semiconductor channel layer.


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