The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 19, 2019

Filed:

Aug. 16, 2017
Applicant:

Japan Display Inc., Tokyo, JP;

Inventors:

Isao Suzumura, Tokyo, JP;

Hajime Watakabe, Tokyo, JP;

Akihiro Hanada, Tokyo, JP;

Hirokazu Watanabe, Tokyo, JP;

Assignee:

Japan Display Inc., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 21/02 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); G03F 7/00 (2006.01); G02F 1/1343 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); H01L 27/32 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1251 (2013.01); G03F 7/00 (2013.01); H01L 21/02675 (2013.01); H01L 27/124 (2013.01); H01L 27/127 (2013.01); H01L 27/1218 (2013.01); H01L 27/1225 (2013.01); H01L 27/1229 (2013.01); H01L 27/1248 (2013.01); H01L 27/1274 (2013.01); H01L 29/42384 (2013.01); H01L 29/66757 (2013.01); H01L 29/66969 (2013.01); H01L 29/78675 (2013.01); H01L 29/78693 (2013.01); G02F 1/1368 (2013.01); G02F 1/134363 (2013.01); G02F 1/136227 (2013.01); G02F 2001/13685 (2013.01); G02F 2202/104 (2013.01); H01L 21/02532 (2013.01); H01L 21/02565 (2013.01); H01L 21/02592 (2013.01); H01L 27/3258 (2013.01); H01L 27/3262 (2013.01); H01L 27/3276 (2013.01); H01L 2227/323 (2013.01);
Abstract

The purpose of the present invention is to form both LTPS TFT and Ply-Si TFT on a same substrate. The feature of the display device to realize the above purpose is that: a display device comprising: a substrate including a first TFT having an oxide semiconductor layer and a second TFT having a Poly-Si layer, an undercoat is formed on the substrate, the oxide semiconductor layer is formed on or above the undercoat, a first interlayer insulating film is formed on or above the oxide semiconductor layer, the Poly-Si layer is formed on or above the first interlayer insulating film.


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