The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 19, 2019

Filed:

Nov. 01, 2016
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Ordos Yuansheng Optoelectronics Co., Ltd., Ordos, Inner Mongolia, CN;

Inventor:

Zuqiang Wang, Beijing, CN;

Assignees:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 27/12 (2006.01); H01L 21/02 (2006.01); H01L 21/265 (2006.01); H01L 21/324 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1222 (2013.01); H01L 21/02532 (2013.01); H01L 21/02595 (2013.01); H01L 21/26513 (2013.01); H01L 21/324 (2013.01); H01L 27/127 (2013.01); H01L 29/66757 (2013.01); H01L 29/78621 (2013.01); H01L 29/78675 (2013.01); H01L 2029/7863 (2013.01);
Abstract

A polysilicon thin film transistor, a manufacturing method thereof, an array substrate involve display technology field, and can repair the boundary defect and the defect state in polysilicon, suppress the hot carrier effect and make the characteristics of TFTs more stable. The polysilicon thin film transistor includes a gate electrode, a source electrode, a drain electrode and an active layer, the active layer comprises at least a channel area, first doped regions, second doped regions and heavily doped regions, and the first doped regions are disposed on two sides of the channel area, the second doped regions are disposed on sides of the first doped regions away from the channel area; the heavily doped regions are disposed on sides of the second doped regions opposed to the first doped regions; and dosage of ions in the heavily doped regions lies between that in the first doped regions and that in the second doped regions.


Find Patent Forward Citations

Wang, Zuqiang. (2019). Polysilicon thin film transistor and manufacturing method thereof, array substrate (U.S. Patent No. 10211229). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10211229

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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