IDiyas

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10211216 B1

PDFFull Text
Date of Patent:
Feb. 19, 2019

Filed:

Apr. 24, 2018

Semiconductor device and method of manufacturing the same

Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventor:

Shibun Tsuda, Tokyo, JP;

Assignee:

RENESAS ELECTRONICS CORPORATION, Tokyo, JP;

Attorney:

McGinn I.P. Law Group, PLLC.

Primary Examiner:

Jack Chen

Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 27/11568 (2017.01); H01L 27/11573 (2017.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 29/792 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01); H01L 27/1157 (2017.01); H01L 21/762 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11568 (2013.01); H01L 21/28282 (2013.01); H01L 21/762 (2013.01); H01L 21/823431 (2013.01); H01L 27/0886 (2013.01); H01L 27/1157 (2013.01); H01L 27/11573 (2013.01); H01L 29/42344 (2013.01); H01L 29/42348 (2013.01); H01L 29/66833 (2013.01); H01L 29/7851 (2013.01); H01L 29/7856 (2013.01); H01L 29/792 (2013.01);
Abstract

A semiconductor device includes a semiconductor substrate including a main surface, a plurality of first projecting portions which include portions of the semiconductor substrate provided in a first region of the semiconductor substrate to extend in a first direction along the main surface of the semiconductor substrate and to be spaced apart from each other in a second direction, orthogonal to the first direction, along the main surface of the semiconductor substrate, a first isolation region provided between the first projecting portions adjacent to each other, and first and second transistors provided in and over an upper part of each of the first projecting portions which is exposed from an upper surface of the first isolation region to be adjacent to each other in the first direction.

Find Patent Forward Citations

Loading…