The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 19, 2019
Filed:
Apr. 27, 2016
International Business Machines Corporation, Armonk, NY (US);
Brent R. Den Hartog, Rochester, MN (US);
Eric J. Lukes, Stewartville, MN (US);
Matthew J. Paschal, Rochester, MN (US);
Nghia V. Phan, Rochester, MN (US);
Raymond A. Richetta, Rochester, MN (US);
Patrick L. Rosno, Rochester, MN (US);
Timothy J. Schmerbeck, Mantorville, MN (US);
Dereje G. Yilma, Rochester, MN (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A circuit component comprises a row of transistors. The row may contain a first active FET with a source region and a drain region. The row may also contain a first active dummy FET that shares the source region and that also has a diffusion region. The row may also contain a second active FET and a second active dummy FET, positioned such that the active dummy FETs are located between the active FETs on the row. The row may also have an end positioned such that the first active dummy FET is between the end and the first active FET. A supply of current may be electrically connected to the source diffusion regions. A load region may be electrically connected to the drain region. The first active FET and the first active dummy FET may have gates that share a voltage source or that have their own voltage source.