The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 19, 2019

Filed:

Jan. 19, 2016
Applicant:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Inventors:

Jinshuang Zhang, Shanghai, CN;

Shengfen Chiu, Shanghai, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/11543 (2017.01); H01L 27/11575 (2017.01); H01L 27/11512 (2017.01); H01L 21/768 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01); H01L 27/11536 (2017.01); H01L 27/11541 (2017.01); H01L 21/285 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76886 (2013.01); H01L 21/28273 (2013.01); H01L 21/28518 (2013.01); H01L 21/76897 (2013.01); H01L 27/11536 (2013.01); H01L 27/11541 (2013.01); H01L 29/665 (2013.01); H01L 29/6656 (2013.01); H01L 29/6659 (2013.01); H01L 29/66825 (2013.01); H01L 29/7881 (2013.01); H01L 21/02063 (2013.01); H01L 21/76843 (2013.01); H01L 21/76855 (2013.01);
Abstract

A method for manufacturing a semiconductor device includes providing a semiconductor substrate having a core region and a peripheral region, and prior to forming a metal silicide in the core region, forming a sidewall layer on opposite sides of a gate structure of a core region device. The sidewall layer includes sequentially, from the inside out, a silicon oxide layer, a first silicon nitride layer, a first silicon nitride layer, a second silicon oxide layer, and a second silicon nitride layer, or the sidewall layer includes, from inside out, a first silicon nitride layer and a second silicon nitride layer. The sidewall layer having such structure ensures that the formed metal silicide has a good morphology in the core region to achieve good device performance.


Find Patent Forward Citations

Zhang, Jinshuang. (2019). Non-volatile memory device and method for manufacturing the same (U.S. Patent No. 10211102). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10211102

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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