The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 19, 2019
Filed:
Mar. 15, 2012
Botond Szatmary, San Diego, CA (US);
Eugene M. Izhikevich, San Diego, CA (US);
Csaba Petre, San Diego, CA (US);
Jayram Moorkanikara Nageswaran, San Diego, CA (US);
Filip Piekniewski, San Diego, CA (US);
Botond Szatmary, San Diego, CA (US);
Eugene M. Izhikevich, San Diego, CA (US);
Csaba Petre, San Diego, CA (US);
Jayram Moorkanikara Nageswaran, San Diego, CA (US);
Filip Piekniewski, San Diego, CA (US);
QUALCOMM Incorporated, San Diego, CA (US);
Abstract
Apparatus and methods for high-level neuromorphic network description (HLND) framework that may be configured to enable users to define neuromorphic network architectures using a unified and unambiguous representation that is both human-readable and machine-interpretable. The framework may be used to define nodes types, node-to-node connection types, instantiate node instances for different node types, and to generate instances of connection types between these nodes. To facilitate framework usage, the HLND format may provide the flexibility required by computational neuroscientists and, at the same time, provides a user-friendly interface for users with limited experience in modeling neurons. The HLND kernel may comprise an interface to Elementary Network Description (END) that is optimized for efficient representation of neuronal systems in hardware-independent manner and enables seamless translation of HLND model description into hardware instructions for execution by various processing modules.