The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 19, 2019

Filed:

Feb. 06, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Venkata N. S. Anumula, Hyderabad, IN;

Madhusudanan Kandasamy, Gobichettipalayam, IN;

Sudhir Maddali, Hyderabad, IN;

Sanket Rathi, Hyderabad, IN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 13/00 (2006.01); G06F 15/167 (2006.01); G06F 3/06 (2006.01); G06F 15/78 (2006.01); G06F 12/1009 (2016.01);
U.S. Cl.
CPC ...
G06F 15/167 (2013.01); G06F 3/067 (2013.01); G06F 3/0613 (2013.01); G06F 3/0659 (2013.01); G06F 15/7889 (2013.01); G06F 12/1009 (2013.01); G06F 2212/154 (2013.01);
Abstract

An approach to virtualizing a coherent memory hardware accelerator is provided comprising creating a segment table for a client logical partition (LPAR), wherein a virtual address space is reserved in the segment table, receiving an Input/Output (I/O) request to use the coherent memory hardware accelerator, generating an I/O operation associated with the I/O request, wherein the I/O operation is passed to the coherent memory hardware accelerator, receiving a map request from the coherent memory hardware accelerator, creating an entry in the reserved virtual address space in the segment table, creating a hardware page table map request for mapping a memory address associated with the client LPAR and returning the reserved virtual address space to the coherent memory hardware accelerator, wherein the coherent memory hardware accelerator has remote direct memory access to memory associated with the client LPAR for performing an acceleration of one or more processes.


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