The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 19, 2019

Filed:

Jun. 30, 2016
Applicant:

Mstar Semiconductor, Inc., Hsinchu Hsien, TW;

Inventors:

Yu-Hsiang Huang, Zhubei, TW;

Jyun-Yang Shih, Zhubei, TW;

Chun-Chia Chen, Zhubei, TW;

Assignee:

MSTAR SEMICONDUCTOR, INC., Hsinchu Hsien, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/687 (2006.01); G05F 1/56 (2006.01); H03K 19/0185 (2006.01);
U.S. Cl.
CPC ...
G05F 1/56 (2013.01); H03K 19/018578 (2013.01); H03K 2217/0036 (2013.01);
Abstract

A low-voltage differential signaling (LVDS) driving circuit, coupled to a load resistor via a first output end and a second output end, includes: a voltage generating unit, providing a first reference voltage; a first switch, coupled between the voltage generating unit and a first node; a second switch, coupled between the voltage generating unit and a second node; a third switch, coupled between the first node and a third node, the third node having a second reference voltage; a fourth switch, coupled between the second node and the third node; a first resistor, coupled between the first node and the first output end; and a second resistor, coupled between the second node and the second output end. The first resistor and the second resistor are in a series connection with the load resistor.


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