The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 12, 2019

Filed:

Feb. 08, 2017
Applicant:

Avago Technologies International Sales Pte. Limited, Singapore, SG;

Inventors:

Mohyee Mikhemar, Irvine, CA (US);

Amir Hadji-Abdolhamid, Aliso Viejo, CA (US);

Hooman Darabi, Laguna Niguel, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03B 1/00 (2006.01); H03H 11/12 (2006.01); H03F 1/02 (2006.01); H04B 1/12 (2006.01); H04B 1/16 (2006.01); H03F 3/19 (2006.01); H03F 3/45 (2006.01); H03G 1/00 (2006.01); H03F 1/08 (2006.01); H03G 3/30 (2006.01); H04L 25/06 (2006.01); H03G 3/32 (2006.01);
U.S. Cl.
CPC ...
H03H 11/1217 (2013.01); H03F 1/0205 (2013.01); H03F 1/086 (2013.01); H03F 3/19 (2013.01); H03F 3/45076 (2013.01); H03G 1/0005 (2013.01); H03G 1/0029 (2013.01); H03G 3/3068 (2013.01); H03G 3/32 (2013.01); H03H 11/1256 (2013.01); H04B 1/123 (2013.01); H04B 1/16 (2013.01); H04L 25/06 (2013.01); H03F 2200/294 (2013.01); H03F 2200/451 (2013.01); H03F 2200/91 (2013.01); H03F 2203/45332 (2013.01); H03F 2203/45336 (2013.01); H03H 11/1252 (2013.01); H03H 11/1291 (2013.01); H03H 2210/025 (2013.01);
Abstract

According to one embodiment, a compact low-power receiver comprises first and second analog circuits connected by a digitally controlled interface circuit. The first analog circuit has a first direct-current (DC) offset and a first common mode voltage at an output, and the second analog circuit has a second DC offset and a second common mode voltage at an input. The digitally controlled interface circuit connects the output to the input, and is configured to match the first and second DC offsets and to match the first and second common mode voltages. In one embodiment, the first analog circuit is a variable gain control transimpedance amplifier (TIA) implemented using a current mode buffer, the second analog circuit is a second-order adjustable low-pass filter, whereby a three-pole adjustable low-pass filter in the compact low-power receiver is effectively produced.


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