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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10205431 B1

PDFFull Text
Date of Patent:
Feb. 12, 2019

Filed:

Jan. 18, 2017

Nonvolatile memory device, memory system including the same and method of operating the same

Applicants:

Dae-woon Kang, Suwon-si, KR;

Jeong-don Ihm, Seongnam-si, KR;

Byung-hoon Jeong, Hwaseong-si, KR;

Young-don Choi, Seoul, KR;

Inventors:

Dae-Woon Kang, Suwon-si, KR;

Jeong-Don Ihm, Seongnam-si, KR;

Byung-Hoon Jeong, Hwaseong-si, KR;

Young-Don Choi, Seoul, KR;

Assignee:

Samsung Electronics Co., Ltd., Gyeonggo-Do, KR;

Attorney:

Harness, Dickey & Pierce, P.L.C.

Primary Examiner:

Vibol Tan

Int. Cl.
CPC ...
H03K 19/0175 (2006.01); G11C 7/00 (2006.01); H03H 7/38 (2006.01); H03K 19/00 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 5/02 (2006.01); G11C 5/04 (2006.01); G11C 7/10 (2006.01); G11C 29/02 (2006.01); G11C 16/04 (2006.01); G11C 29/50 (2006.01);
U.S. Cl.
CPC ...
H03H 7/38 (2013.01); G11C 5/025 (2013.01); G11C 5/04 (2013.01); G11C 7/1057 (2013.01); G11C 7/1084 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 29/022 (2013.01); G11C 29/028 (2013.01); H03K 19/0005 (2013.01); H03K 19/017545 (2013.01); G11C 16/0483 (2013.01); G11C 29/025 (2013.01); G11C 29/50008 (2013.01); G11C 2207/105 (2013.01);
Abstract

A nonvolatile memory device includes a first memory structure. The first memory structure includes first through N-th memory dies that may be connected to an external memory controller via a first channel. N is a natural number equal to or greater than two. At least one of the first through N-th memory dies is configured to be used as a first representative die that performs an on-die termination (ODT) operation while a data write operation is performed for one of the first through N-th memory dies.

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