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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10205016 B1

PDFFull Text
Date of Patent:
Feb. 12, 2019

Filed:

Apr. 11, 2017

Method for manufacturing an integrated circuit including a lateral trench transistor and a logic circuit element

Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Andreas Meiser, Sauerlach, DE;

Till Schloesser, München, DE;

Detlef Weber, Ottendorf-Okrilla, DE;

Karl-Heinz Gebhardt, Dresden, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:

Murphy, Bilak & Homiller, PLLC

Primary Examiner:

Dale E Page

Assistant Examiner:

Wasiul Haider

Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 27/088 (2006.01); H01L 29/417 (2006.01); H01L 21/8234 (2006.01); H01L 21/265 (2006.01); H01L 29/40 (2006.01); H01L 29/10 (2006.01); H01L 27/06 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7825 (2013.01); H01L 21/823418 (2013.01); H01L 27/088 (2013.01); H01L 29/41758 (2013.01); H01L 29/41766 (2013.01); H01L 29/66659 (2013.01); H01L 29/66696 (2013.01); H01L 29/66704 (2013.01); H01L 29/7835 (2013.01); H01L 21/26586 (2013.01); H01L 27/0623 (2013.01); H01L 27/0922 (2013.01); H01L 29/1095 (2013.01); H01L 29/404 (2013.01); H01L 29/407 (2013.01);
Abstract

A method of forming an integrated circuit includes forming gate trenches in the first main surface of a semiconductor substrate, the gate trenches being formed so that a longitudinal axis of the gate trenches runs in a first direction parallel to the first main surface. The method further includes forming a source contact groove running in a second direction parallel to the first main surface, the second direction being perpendicular to the first direction, the source contact groove extending along the plurality of gate trenches, forming a source region including performing a doping process to introduce dopants through a sidewall of the source contact groove, and filling a sacrificial material in the source contact groove. The method also includes, thereafter, forming components of the logic circuit element, thereafter, removing the sacrificial material from the source contact groove, and filling a source conductive material in the source contact groove.

Find Patent Forward Citations

Meiser, Andreas. (2019). Method for manufacturing an integrated circuit including a lateral trench transistor and a logic circuit element (U.S. Patent No. 10205016). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10205016

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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