The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 12, 2019

Filed:

Nov. 28, 2016
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Simone Lavanga, Faak am See, AT;

Marco Silvestri, Bodensdorf, AT;

Gilberto Curatola, Villach, AT;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/308 (2006.01); H01L 29/423 (2006.01); H01L 21/306 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/40 (2006.01); H01L 29/66 (2006.01); H01L 29/778 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42316 (2013.01); H01L 21/308 (2013.01); H01L 21/30621 (2013.01); H01L 29/1066 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/401 (2013.01); H01L 29/66462 (2013.01); H01L 29/7786 (2013.01); H01L 29/7787 (2013.01);
Abstract

A heterostructure body with a buffer region, and a barrier region disposed on the buffer region is provided. A gate trench is formed in the barrier region. A layer of doped semiconductor material that fills the gate trench is formed. The doped semiconductor material in the gate trench locally depletes a subjacent section of the two-dimensional charge carrier gas channel at zero bias. A layer of electrically conductive material is formed on the doped semiconductor material. The layer of doped semiconductor material is structured to form a gate structure that includes a narrower portion of the doped semiconductor material that is disposed in the gate trench, a wider portion of the doped semiconductor material that is above the trench, and a gate electrode portion of the electrically conductive material that completely covers the wider portion of the doped semiconductor material.


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