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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10204980 B1

PDFFull Text
Date of Patent:
Feb. 12, 2019

Filed:

May. 23, 2017

Semiconductor device and manufacturing method of the same

Applicants:

Toyota Jidosha Kabushiki Kaisha, Toyota-shi, Aichi-ken, JP;

Denso Corporation, Kariya-shi, Aichi-ken, JP;

Inventors:

Yoshifumi Yasuda, Nagoya, JP;

Tatsuji Nagaoka, Nagakute, JP;

Yasushi Urakami, Kariya, JP;

Sachiko Aoi, Nagakute, JP;

Assignees:

TOYOTA JIDOSHA KABUSHIKI KAISHA, Toyota, JP;

DENSO CORPORATION, Kariya, JP;

Attorney:

Oliff PLC

Primary Examiner:

Lynne Gurley

Assistant Examiner:

Vernon P Webb

Int. Cl.
CPC ...
H01L 21/26 (2006.01); H01L 29/06 (2006.01); H01L 29/41 (2006.01); H01L 29/66 (2006.01); H01L 21/265 (2006.01); H01L 29/417 (2006.01); H01L 29/872 (2006.01); H01L 29/16 (2006.01); H01L 21/04 (2006.01); H01L 29/739 (2006.01); H01L 29/78 (2006.01); H01L 29/861 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0619 (2013.01); H01L 21/0465 (2013.01); H01L 21/26513 (2013.01); H01L 21/26586 (2013.01); H01L 29/0688 (2013.01); H01L 29/0692 (2013.01); H01L 29/1608 (2013.01); H01L 29/417 (2013.01); H01L 29/66143 (2013.01); H01L 29/872 (2013.01); H01L 29/6606 (2013.01); H01L 29/66136 (2013.01); H01L 29/66333 (2013.01); H01L 29/66712 (2013.01); H01L 29/7395 (2013.01); H01L 29/7811 (2013.01); H01L 29/861 (2013.01);
Abstract

A semiconductor device may include an element region and a peripheral voltage withstanding region. The peripheral voltage withstanding region includes inner circumferential guard rings; and outer circumferential guard rings having a width narrower than a width of the inner circumferential guard rings. An interval between the inner circumferential guard rings is narrower than an interval between the outer circumferential guard rings. Each of the inner circumferential guard rings includes a first high concentration region and a first low concentration region. Each of the outer circumferential guard rings includes a second high concentration region and a second low concentration region. A width of a part of each first low concentration region that is exposed on a front surface of the semiconductor device is wider than a width of a part of each second low concentration region that is exposed on the front surface.

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