The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10204932 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 12, 2019

Filed:

Oct. 19, 2015
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Hefei Boe Optoelectronics Technology Co., Ltd., Hefei, Anhui, CN;

Inventor:

Lijuan Yang, Beijing, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/84 (2006.01); H01L 27/12 (2006.01); G03F 7/00 (2006.01); H01L 21/77 (2017.01); G03F 7/42 (2006.01); H01L 21/027 (2006.01); G02F 1/1362 (2006.01); H01L 27/32 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1244 (2013.01); G03F 7/00 (2013.01); G03F 7/0005 (2013.01); G03F 7/0035 (2013.01); G03F 7/42 (2013.01); H01L 21/0274 (2013.01); H01L 21/77 (2013.01); H01L 27/12 (2013.01); H01L 27/1262 (2013.01); H01L 27/1288 (2013.01); G02F 1/136286 (2013.01); G02F 2001/136295 (2013.01); H01L 27/3276 (2013.01);
Abstract

An array substrate and a manufacturing method thereof are provided. The array substrate includes a display area () and a fan-out area () disposed at the periphery of the display area (), the manufacturing method comprising forming a line pattern () disposed in at least one of the display area () and the fan-out area (), wherein forming a line pattern disposed in at least one of the display area and the fan-out area includes the following steps: forming a metal layer (); forming an intermediate pattern () by performing a first patterning process on the metal layer; and forming the line pattern disposed in at least one of the display area () and the fan-out area () by performing a second patterning process on the intermediate pattern. The manufacturing methods provided by the respective embodiment of the present disclosure are capable of narrowing of the lines in the fan-out area, and compared with the existing one exposure method, can effectively reduce the risk of open-circuit and short-circuit.


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Yang, Lijuan. (2019). Array substrate, manufacturing method thereof, display panel and display device (U.S. Patent No. 10204932). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10204932

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