The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10204904 B1

Date of Patent:

Feb. 12, 2019

Filed:

May. 10, 2017

Methods, apparatus and system for vertical finfet device with reduced parasitic capacitance

Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Hui Zang, Guilderland, NY (US);

Rinus Tek Po Lee, Ballston Spa, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorney:

Williams Morgan, P.C.

Primary Examiner:

Hrayr A Sayadian

Int. Cl.

CPC ...

H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 21/764 (2006.01);

U.S. Cl.

CPC ...

H01L 27/0886 (2013.01); H01L 21/764 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823462 (2013.01); H01L 21/823468 (2013.01); H01L 21/823481 (2013.01);

Abstract

A method, apparatus and system are disclosed herein for a finFET device having an air gap spacer and/or a tapered bottom dielectric spacer for reducing parasitic capacitance. A first source/drain (S/D) region is formed on a substrate. A set of fin structures are formed above the first S/D region. A gate region is formed above the first S/D region and adjacent at least a portion of the fin structures. A space for an air gap is formed above the gate region. A top epitaxial (EPI) feature is formed extending over the space for the air gap, thereby forming an air gap spacer between the top epitaxial feature and the gate region.

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