The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 12, 2019
Filed:
Sep. 08, 2016
Applicant:
Arm Limited, Cambridge, GB;
Inventor:
Marlin Wayne Frederick, Jr., Austin, TX (US);
Assignee:
ARM Limited, Cambridge, GB;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 21/4763 (2006.01); G06F 17/50 (2006.01); H01L 27/02 (2006.01); H01L 23/528 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0207 (2013.01); G06F 17/5068 (2013.01); G06F 17/5077 (2013.01); G06F 17/5081 (2013.01); H01L 21/76816 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/5286 (2013.01); H01L 27/0203 (2013.01); G06F 2217/06 (2013.01); H01L 2924/0002 (2013.01);
Abstract
An integrated circuit layout includes a routing layout of routing conductors and routing connection vias formed prior to a power grid connection which forms power connection vias between power grid conductors and standard-power cell conductors within the standard cells. This enables a minimum via spacing requirement to be met while permitting an increased flexibility in the positioning of the routing connection vias.