The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 12, 2019

Filed:

Nov. 08, 2016
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Beijing Boe Display Technology Co., Ltd., Beijing, CN;

Inventors:

Yingqiang Gao, Beijing, CN;

Xiaopeng Cui, Beijing, CN;

Dongliang Wang, Beijing, CN;

Xingliang Li, Beijing, CN;

Ruirui Wang, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 19/00 (2006.01); G11C 19/28 (2006.01); G09G 3/20 (2006.01); G11C 19/18 (2006.01); G09G 3/36 (2006.01);
U.S. Cl.
CPC ...
G11C 19/28 (2013.01); G09G 3/2003 (2013.01); G11C 19/184 (2013.01); G09G 3/3677 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/061 (2013.01); G09G 2320/0219 (2013.01);
Abstract

The present application discloses a shift register unit circuit including an input port for receiving an input signal, an output port for outputting a gate driving signal, a first clock input port for receiving a first clock signal, a second clock input port for receiving a second clock signal, a pull-up node, a first pull-down node, a second pull-down node, a pull-up control sub-circuit connected to the input port and the pull-up node, a pull-up sub-circuit connected to the first clock input port and the pull-up node, a pull-down control sub-circuit connected to the first clock input port, a pull-down sub-circuit connected to the first pull-down node and the second pull-down node, a reset sub-circuit receiving a reset signal to control the potential level at the second pull-down node, and an initialization sub-circuit configured to receive an enabling signal for pulling-down the potential level at the second pull-down node.


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