The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 12, 2019

Filed:

Aug. 03, 2018
Applicant:

SK Hynix Inc., Incheon-si, Gyeonggi-do, KR;

Inventors:

Keun Soo Song, Icheon-si, KR;

Woo Yeol Shin, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/18 (2006.01); G11C 7/22 (2006.01); G11C 7/10 (2006.01); G06F 13/42 (2006.01); G11C 8/06 (2006.01);
U.S. Cl.
CPC ...
G11C 8/18 (2013.01); G06F 13/4234 (2013.01); G11C 7/1066 (2013.01); G11C 7/1093 (2013.01); G11C 7/222 (2013.01); G11C 8/06 (2013.01);
Abstract

A semiconductor system may include a controller configured to provide a first external clock and a control signal to a semiconductor device, and the semiconductor device configured to transmit/receive external data and a plurality of second external clocks to/from the controller, wherein the plurality of second external clocks comprise a third primary external clock and a third secondary external clock, and the semiconductor device transmits both of the third primary external clock and the third secondary external clock to the controller or transmits one of the third primary external clock and the third secondary external clock to the controller, based on an operation select signal.


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