The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 12, 2019

Filed:

Mar. 02, 2015
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Manabu Matsumoto, Yokohama Kanagawa, JP;

Isao Ozawa, Chigasaki Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/18 (2006.01); G11C 5/02 (2006.01); H01L 25/18 (2006.01); G11C 29/08 (2006.01); G11C 29/12 (2006.01); H05K 1/02 (2006.01); H05K 1/11 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 5/025 (2013.01); G11C 29/08 (2013.01); G11C 29/1201 (2013.01); H01L 25/18 (2013.01); H05K 1/0268 (2013.01); H05K 1/113 (2013.01); G11C 16/0483 (2013.01); H01L 23/3128 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 25/0657 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48145 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/06562 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01); H05K 2201/10159 (2013.01); H05K 2201/10734 (2013.01);
Abstract

A semiconductor device includes a printed circuit board having a first surface and a second surface on a side opposite to the first surface. First pads are on the first surface of the printed circuit board. An interface part is mounted on the printed circuit board via the first pads and is configured to transfer a signal between the interface part and a host device. Second pads are also on the first surface and insulated from the interface part. A semiconductor memory and a controller are mounted on the first surface. First solder balls electrically connect the first pads and the controller. Second solder balls electrical connect the second pads and the controller. A plurality of third pads are disposed on the second surface and electrically connected to the second pads allowing direct connections to the controller and memory via the second pads.


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