The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 12, 2019
Filed:
Sep. 07, 2017
Applicant:
Microunity Systems Engineering, Inc., Santa Clara, CA (US);
Inventors:
Craig Hansen, Los Altos, CA (US);
John Moussouris, San Francisco, CA (US);
Alexia Massalin, San Jose, CA (US);
Assignee:
MicroUnity Systems Engineering, Inc., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 9/30 (2018.01); G06F 12/0875 (2016.01); G06F 9/34 (2018.01); G06F 9/38 (2018.01);
U.S. Cl.
CPC ...
G06F 12/0875 (2013.01); G06F 9/3016 (2013.01); G06F 9/30181 (2013.01); G06F 9/30192 (2013.01); G06F 9/34 (2013.01); G06F 9/3824 (2013.01); G06F 9/3895 (2013.01); G06F 2212/452 (2013.01);
Abstract
Expandably wide operations are disclosed in which operands wider than the data path between a processor and memory are used in executing instructions. The expandably wide operands reduce the influence of the characteristics of the associated processor in the design of functional units performing calculations, including the width of the register file, the processor clock rate, the exception subsystem of the processor, and the sequence of operations in loading and use of the operand in a wide cache memory.